Function Table

H

= HIGH Level (steady state)

L

= LOW Level (steady state)

X

= Don’t Care (any input, including transitions)

↑ = Transition from LOW-to-HIGH level

a, b, c, d

= The level of steady state input at inputs A, B, C or D, respectively.

QA0, QB0, QC0, QD0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.

QAn, QBn, QCn, QDn = The level of QA, QB, QC, respectively, before the most-recent ↑ transition of the clock.

Logic Diagram

Inputs

Outputs

Clear

Mode

Clock

Serial

Parallel

QA

QB

QC

QD

S1

S0

Left

Right

A

B

C

D

L

X

X

X

X

X

XX

XX

L

L

L

L

H

X

X

L

X

X

XX

XX

QA0

QB0

QC0

QD0

HH

H

↑

XX

a

b

c

d

a

b

c

d

HL

H

↑

X

H

XX

XX

H

QAn

QBn

QCn

HL

H

↑

X

L

XX

XX

L

QAn

QBn

QCn

HH

L

↑

H

X

XX

XX

QBn

QCn

QDn

H

HH

L

↑

L

X

XX

XX

QBn

QCn

QDn

L

H

L

L

X

X

X

XX

XX

QA0

QB0

QC0

QD0

www.sycelectronica.com.ar