RT9218BGS datasheet(13/17 Pages) RICHTEK

13 / 17 page

RT9218B

DS9218B-09 March 2007

www.richtek.com

There are two sets of critical components in a DC-DC

converter using the RT9218B. The switching power

components are most critical because they switch large

amounts of energy, and as such, they tend to generate

equally large amounts of noise. The critical small signal

components are those connected to sensitive nodes or

those supplying critical bypass current.

The power components and the PWM controller should

be placed firstly. Place the input capacitors, especially the

high-frequency ceramic decoupling capacitors, close to the

power switches. Place the output inductor and output

capacitors between the MOSFETs and the load. Also locate

the PWM controller near by MOSFETs.

A multi-layer printed circuit board is recommended.

PWM Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency and radiate noise, that results

in over-voltage stress on devices. Careful component

placement layout and printed circuit design can minimize

the voltage spikes induced in the converter. Consider, as

an example, the turn-off transition of the upper MOSFET

prior to turn-off, the upper MOSFET was carrying the full

load current. During turn-off, current stops flowing in the

upper MOSFET and is picked up by the low side MOSFET

or schottky diode. Any inductance in the switched current

path generates a large voltage spike during the switching

interval. Careful component selections, layout of the critical

components, and use shorter and wider PCB traces help

in minimizing the magnitude of voltage spikes.

Figure 7. UV and OC trigger hiccup mode

TIME

COUNT = 1

COUNT = 2

OVERLOAD

APPLIED

COUNT = 3

COUNT = 4

Figure 8, UV_FB trigger VIN power sensing

Power Off

Time (10ms/Div)

UGATE

(20V/Div)

VOUT

VIN

(500mV/Div)

(2V/Div)

VIN Power

Sensing

IOUT = 2A

LDO Power Sequence

In VGA field, the MOSFET of LVOUT is sourced by external

voltage not by SVOUT.

This connection may trigger UV protection to shutdown

RT9218B, but using the typical application circuit won't

have this issue. See figure 9 using OPS pin to control the

power sequence.

VIN_SW (5V/12V)

VIN_LDO (3.3V)

OPS_Disable

Enable

Shutdown

Figure 9. LDO power sequence

Under Voltage Protection

The voltage at FB and FBL pin is monitored and protected

against UV (under voltage). The UV threshold is the FB or

FBL under 75%. UV detection has 30

μs triggered delay.

When OC or UV_FBL is trigged, a hiccup restart sequence

will be initialized, as shown in Figure 7 Only 4 times of

trigger are allowed to latch off. Hiccup is disabled during

soft-start interval, but UV_FB has some difference from

OC and UV_FBL, it will always trigger VIN power sensing

after 4 times hiccup, as shown in Figure 8.

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