King Billion Electronics Co., Ltd

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HE84770

HE80000 SERIES

August 25, 2003

Page 21 of 30

V2.6E

This specification is subject to change without notice. Please contact sales person for the latest version before use.

with the value of T2H and T2L.

Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value

of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when

system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and

value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value

should be set before enabling Timer2.

T2H

T2L

"Timer2 Counter"

decreases 1

Count TO

0xFFFFh

Auto reload when

Timer2 underflow

No

Start Timer2

Interrupt Request.

Yes

The contents of T2H and

T2L almost loaded into

Timer2 immediately

when Timer2 is turned on

after reset.

T2_INT

The Timer2 related control registers are list as below:

Register Address

Field

Bit position Mode

Description

IER

0x02

TC2_IER

1

R/W 0: TC2 interrupt is disabled. (default)

1: TC2 interrupt is enabled.

T2L

0x05

T2L[7:0]

7~0

W

Low byte of TC2 pre-load value

T2H

0x06

T2H[7:0]

7~0

W

High byte of TC2 pre-load value

OP1

0x09

TC2E

3

R/W 0: TC2 is disabled. (default)

1: TC2 is enabled.