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74LVC2G74DP Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC2G74DP Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 19 page ![]() 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 3 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 6. Pinning information 6.1 Pinning Fig 3. Logic diagram mna421 SD CP RD D C C Q C C C C C C Q C C Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74LVC2G74 CP VCC DSD QRD GND Q 001aaf642 1 2 3 4 6 5 8 7 Fig 5. Pin configuration SOT833-1 (XSON8) Fig 6. Pin configuration SOT902-1 (XQFN8) 74LVC2G74 RD SD VCC Q Q D CP GND 001aaf643 36 27 18 45 Transparent top view 001aaf644 D RD CP Q SD Q Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2G74 |
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