IIS2DULPX datasheet(47/106 Pages) STMICROELECTRONICS

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8.11

FIFO_WTM (16h)

R/W

Table 43. FIFO_WTM register

XL_ONLY

_FIFO

FTH6

FTH5

FTH4

FTH3

FTH2

FTH1

FTH0

Table 44. FIFO_WTM register description

XL_ONLY_FIFO

FIFO data configuration.

If this bit is set to 0 (default), accelerometer data and temperature/AH/Qvar data are stored in FIFO.

If this bit is set to 1, only accelerometer data are stored in FIFO.

FTH[6:0]

FIFO watermark threshold, maximum value is 127.

8.12

INTERRUPT_CFG (17h)

R/W

Table 45. INTERRUPT_CFG register

TIMESTAMP

_EN

0(1)

WAKE_

THS_W

0(1)

SLEEP_STAT

US_ON_INT

DIS_RST_LIR

_ALL_INT

LIR

INTERRUPTS

_ENABLE

1. This bit must be set to 0 for the correct operation of the device.

Table 46. INTERRUPT_CFG register description

TIMESTAMP_EN

Enables timestamp counter. The counter is readable in TIMESTAMP0 (7Ah), TIMESTAMP1

(7Bh), TIMESTAMP2 (7Ch), and TIMESTAMP3 (7Dh). Default value: 0

(0: disabled; 1: enabled)

WAKE_THS_W

Weight of 1 LSB of wake-up threshold. Default value: 0

(0: 1 LSB = FS_XL / (26);

1: 1 LSB = FS_XL / (28) )

SLEEP_STATUS_ON_INT

Sends the sleep status instead of sleep change to INT pins

(only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, respectively in

registers MD1_CFG (1Fh) and MD2_CFG (20h)). Default value: 0

(0: sleep change on INT pins; 1: sleep status on INT pins)

DIS_RST_LIR_ALL_INT

If 1, disables the reset of the interrupt flags when ALL_INT_SRC (24h) is read.

LIR

Interrupt mode configuration (see Table 9). Default value: 0

(0: interrupt level mode; 1: interrupt latched mode)

INTERRUPTS_ ENABLE

Enables basic interrupts (6D/4D, free-fall, wake-up, single/double/triple-tap, activity/inactivity).

Default value: 0

(0: interrupt disabled; 1: interrupt enabled)

IIS2DULPX

DS14580 - Rev 1

page 47/106

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