TMPR4937 datasheet(49/552 Pages) TOSHIBA

49 / 552 page

Chapter 1 Overview and Features

1-3

(2) Direct Memory Access Controllers (DMAC)

The TX4937 has two DMA Controllers for invoking DMA transfer with memory and I/O

devices. Each DMA Controller has 4 built-in DMA Channels.

•

Can set internal/external DMA requests

•

Supports as internal DMA requests DMA with the on-chip Serial I/O Controller or AC-link

Controller

•

Supports as external I/O DMA transfer modes using external DMA requests Single Address

transfer (Fly-by DMA) and Dual Address transfer

•

Supports transfer between external devices with a data bus width of 32 bits, 16 bits or 8 bits

and memory

•

Supports memory-memory copy mode that has no address boundary constraints

Can perform Burst transfer of up to 8 double words in a single read or write operation

•

Supports the Memory Fill mode that writes double-word data to the memory region

•

Supports Chain DMA transfer

(3) SDRAM Controller (SDRAMC)

The SDRAM Controller generates the control signals required for the SDRAM interface. By

having 4 on-chip channels and supporting a variety of memory configurations, the SDRAM

Controller can support memory sizes of up to 4 GB (1 GB/channel).

•

Memory clock (SDCLK) frequencies from 50 MHz to 133 MHz (For relationship between

CPU clock and memory clock, see Section 6.1)

•

4 sets of independent memory channels

•

Supports 2-bank or 4-bank 16 MB, 64 MB, 128 MB, 256 MB, or 512 MB SDRAM

•

Can used Registered DIMM

•

Supports ECC or parity generation/check functions

•

Can select either 32-bit or 64-bit data bus width for each channel

•

Can set SDRAM timing for each channel

•

Supports TX49/H3 core critical word first access

•

Low power consumption mode: can select Self-refresh or Pre-charge power down

(4) PCI Controller (PCIC)

The TX4937 has an on-chip PCI Controller that is compliant with PCI Local Bus Specification

Revision 2.2.

•

PCI Local Bus Specification Revision 2.2 compliant

•

32-bit PCI interface with maximum PCI Bus clock frequency of 66 MHz

•

Supports both the Target and Initiator functions

•

Can change the address mapping between the internal bus and PCI Bus

•

Has an on-chip PCI Bus arbiter and can connect up to 4 External Bus Masters

•

Has a function mounted for booting the TX4937 from memory on the PCI Bus

•

Has an on-chip 1-channel PCI Controller-dedicated DMA Controller (PDMAC)

TMPR4937 Datasheet(PDF) 49 Page - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 49 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL