TMP93CS32F datasheet(12/180 Pages) TOSHIBA

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TMP93CS32

2004-02-10

93CS32-10

3.3

Standby Function

Standby control circuits consist of (1) System clock controller, (2) Prescaler clock controller

and (3) Standby controller.

Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows the block diagram.

Figure 3.3.3 shows I/O registers. Table 3.3.1 shows the internal operation and system clock.

Figure 3.3.1 Transition Figure

The clock frequency input from X1, X2 pin is called fc. The clock frequency selected by

SYSCR1<GEAR2:0> is called system clock fFPH. The devided clock of fFPH is called system clock

fSYS, and the 1 cycle of fSYS is called 1 state operating mode.

Table 3.3.1 Internal Operation and System Clock

Operating

Mode

Oscillator

CPU

Internal I/O

System Clock

fSYS

RESET

Reset

fc/32

NORMAL

Operate

RUN

Operate

IDLE2

Stop only AD

IDLE1

Oscillation

Programmable

(fc/2, fc/4, fc/8,

fc/16, fc/32)

STOP

Stop

Reset

NORMAL mode

(fc/gear value/2)

RUN mode

(Stops only CPU)

IDLE2 mode

(Stops CPU and AD)

Interrupt

IDLE1 mode

(Operates only oscillator)

Instruction

Interrupt

Instruction

Interrupt

Instruction

Release reset

Interrupt

Instruction

STOP mode

(Stops all circuits)

TMP93CS32F Datasheet(PDF) 12 Page - Toshiba Semiconductor

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