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BLOCK DIAGRAM

Control Unit

- Performs the core synchroni-

zation and data flow control. This module

manages execution of all instructions. The

Control Unit also manages execution of STOP

instruction and waking-up the processor from

the STOP mode.

Opcode Decoder

- Performs an instruction

opcode decoding and the control functions for

all other blocks.

ALU

- Arithmetic Logic Unit performs the

arithmetic and logic operations during execu-

tion of an instruction. Contains accumulator

(A, B), Condition Code Register (CCREG),

Index registers X, Y and related logic such as

arithmetic and logic unit, and multiplier/divider.

Bus Controller

– Program Memory, Data

Memory & SFR’s (Special Function Register)

interface controls access into the program and

data memories and special registers. It con-

tains Program Counter (PC), Stack Pointer

(SP) register, INIT register (INIT), Data Page

Pointer (DPP), and related logic.

Interrupt Controller

- DF6811 extended IC

has implemented 17-level interrupt priority

control. The interrupt requests may come from

external pins (IRQ and XIRQ) as well as from

particular peripherals. The DF6811 peripheral

systems generate maskable interrupts, which

are recognized only if the global interrupt

mask bit (I) in the CCR is cleared. Maskable

interrupts are prioritized according to default

arrangement (look at the table below) estab-

lished during reset. However any one source

may be elevated to the highest maskable pri-

ority position using HPRIO register. When

interrupt condition occurs, an interrupt status

flag is set to indicate the condition.

I/O Ports

- All ports are 8-bit general-purpose

bi-directional

I/O

system.

The

PORTA,

PORTB, PORTC, PORTD data registers have

their corresponding data direction registers

DDRA, DDRB, DDRC, DDRD to control ports

data flow. It assures that all DF6811’s ports

have full I/O selectable registers. Writes to

any ports pins cause data to be stored in the

data registers. If any port pins are configured

as output then data registers are driven out of

those pins. Reads from port pins configured

as input causes that input pin is read. If port

pins is configured as output, during read data

register is read. Writes to any ports pins not

configured as outputs do not cause data to be

driven out of those pins, but the data is stored

in the output registers. Thus, if the pins later

become outputs, the last data written to port

will be driven out the port pins.

portao

portdo

portco

portbo

iromdata

clk

por

cmf

datao

cap1

cap2

cap3

BUS

Controller

I/O

Ports

Opcode

Decoder

Control

Unit

Interrupt

Controller

Timer

with

Compare /

Capture

Unit

SCI Unit

SPI Unit

irq

cmp1

cmp2

cmp3

cmp4

cmp5

cmp1en

cmp2en

cmp3en

cmp4en

cmp5en

txd

rxd

mo

so

si

scki

mi

scko

scken

xirq

iromoe

iromwe

iromaddr

ss

halt

portai

portdi

portci

portbi

lir

ddra

ddrd

ddrc

ddrb

Watchdog

Timer

Pulse

Accumulator

pai

ALU

ready

DoCD

TM

Debugger

docdclk

docddatai

docddatao

clkdocd

iramdata

iramwe

iramaddr

iramoe

xramdata

xramwe

xramaddr

xramoe

ufrdata

ufrwe

ufraddr

ufroe

moda

soen

dataen

modb

Timer, Compare Capture & COP Watchdog

- This timer system is based on a free-running

16-bit counter with a 4-stage programmable

prescaler. A timer overflow function allows

software to extend the timing capability of the

system beyond the 16-bit range of the coun-

ter. Three independent input-capture functions

are used to automatically record the time

when a selected transition is detected at a

respective timer input pin. Five output-