KSZ9567R datasheet(71/233 Pages) MICROCHIP

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DS00002329E-page 71

KSZ9567R

5.1.1.5

PME Pin Control Register

5.1.1.6

Global Interrupt Status Register

This register provides the top level interrupt status for the LUE and GPIO trigger and timestamp functions. These inter-

rupts are enabled in the Global Interrupt Mask Register. For port specific interrupts, refer to the Port Interrupt Status

Address:

0x0006

Size:

8 bits

Bits

Description

Type

Default

7:2

RESERVED

PME Pin Output Enable

0 = Disabled

1 = Enabled

R/W

PME Pin Output Polarity

0 = PME is active low

1 = PME is active high

R/W

Address:

0x0010 - 0x0013

Size:

32 bits

Bits

Description

Type

Default

Lookup Engine (LUE) Interrupt Status

Refer to the Address Lookup Table Interrupt Register for detailed LUE

interrupt status bits.

0 = No interrupt

1 = Interrupt request

GPIO Pin Output Trigger and Timestamp Unit Interrupt Status

Refer to the GPIO Status Monitor 1 Register to determine whether it is a

Trigger Output Unit interrupt or a Timestamp Unit interrupt.

For the interrupt status for the port-based time stamping of PTP egress

frames, refer to the Port Interrupt Status Register and Port PTP Timestamp

Interrupt Status Register.

0 = No interrupt

1 = Interrupt request

29:0

APB Timout Interrupt Status

0 = Interrupt enabled

1 = Interrupt disabled

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