M58BW016DB datasheet(18/69 Pages) STMICROELECTRONICS

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Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

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Bus operations

Each bus operation that controls the memory is described in this section, see Table 4,

Table 5 and Table 6 Bus operations, for a summary. The bus operation is selected through

the Burst Configuration Register; the bits in this register are described at the end of this

section.

On power-up or after a hardware reset the memory defaults to Asynchronous Bus Read and

Asynchronous Bus Write, no other bus operation can be performed until the Burst Control

The electronic signature, CFI or Status Register will be read in asynchronous mode

regardless of the Burst Control Register settings.

Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

3.1

Asynchronous Bus operations

For asynchronous bus operations refer to Table 4 together with the following text.

3.1.1

Asynchronous Bus Read

Asynchronous Bus Read operations read from the memory cells, or specific registers

(electronic signature, Status Register, CFI and Burst Configuration Register) in the

command interface. A valid bus operation involves setting the desired address on the

address inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping

Write Enable and Output Disable High, VIH. The Data inputs/outputs will output the value,

see Figure 8: Asynchronous Bus Read AC waveforms, and Table 16: Asynchronous Bus

Read AC characteristics, for details of when the output becomes valid.

Asynchronous Read is the default read mode which the device enters on power-up or on

return from Reset/Power-down.

3.1.2

Asynchronous Latch Controlled Bus Read

Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific

registers in the command interface. The address is latched in the memory before the value

is output on the data bus, allowing the address to change during the cycle without affecting

the address that the memory uses.

A valid bus operation involves setting the desired address on the address inputs, setting

Chip Enable and Latch Enable Low, VIL and keeping Write Enable High, VIH; the address is

latched on the rising edge of Latch Enable. Once latched, the address inputs can change.

Set Output Enable Low, VIL, to read the data on the Data inputs/outputs; see Figure 9:

Asynchronous Latch Controlled Bus Read AC waveforms, and Table 17: Asynchronous

Latch Controlled Bus Read AC characteristics, for details on when the output becomes

valid.

Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus

Read operations can be performed when the memory is configured for Asynchronous Latch

Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation.

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