TB62802FG

2006-06-14

6

Ta

Ta

= 0 to 60°C

5.5 V

Characteristic

Symbol

Test Condition

Min

Typ.

Max

Min

Max

Unit

Reference

Measurement

Diagram

tpLH (

φ)

5.3

10.8

15.5

5.0

16.0

tpHL (

φ)

5.3

9.8

15.5

5.0

16.0

Measurement

diagram 1

tpLH (O)

2.5

5.4

9.5

2.0

10.0

Propagation delay time

tpHL (O)

2.5

6.0

10.5

2.0

12.0

ns

Measurement

diagram 2

tpCLH (

φ)

9.5

14.0

24.0

9.0

25.0

tpCHL (

φ)

9.5

15.4

24.0

9.0

25.0

Measurement

diagram 1

tpCLH (O)

7.2

10.7

19.0

6.0

23.0

Output OFF time

tpCHL (O)

7.3

18.5

30.0

6.0

35.0

ns

Measurement

diagram 2

Light load drive output

skew

to (skw)

0

⎯

2.0

0

2.0

ns

Measurement

diagram 3

Heavy load drive

output crosspoints

VT (crs)

250 pF

1.5

⎯

⎯

1.5

⎯

V

Measurement

diagram 4

CPD (

φ)

⎯

57

⎯

⎯

⎯

Equivalent internal

capacitance

(Note 1)

CPD (O)

⎯

18

⎯

⎯

⎯

pF

Note 1: CPD denotes “power dissipation capacitance”. Dynamic power dissipation can be calculated using the CPD

value.

Pd

CC

CL: Load capacitance per output

CPD: Power dissipation capacitance

Fin: Input clock frequency

Fout: Output clock frequency

For example:

For heavy load drive output, driving a load capacity of 250 pF at 25 MHz;

For light load drive output, driving a load capacity of 20 pF at 25 MHz.

Note 2: In practice, the frequencies of some shift gate control signals are lower than the transfer clock. Therefore

the power dissipation during practical use is smaller than the calculated value below.

Pd

= [57 pF × 5.0 V × 5.0 V × 25 MHz] × 4 bit + (250 pF × 5.0 V × 5.0 V × 25 MHz) × 4 bit

+ [18 pF × 5.0 V × 5.0 V × 25 MHz] × 4 bit + (20 pF × 5.0 V × 5.0 V × 25 MHz) × 4 bit

∼− 862 mW

The typical power dissipation is approximately 862 mW.

Notes on System Design

As shown above, the TB62802FG consumes high current while operating. There is temporary flow of a current

greater than the calculated value. To suppress bouncing from the power supply and GND, decoupling for the power

supply is a vital necessity.

Below is an example of how the capacitance of a decoupling capacitor is calculated. Be sure to refer to this when

designing a system.

The decoupling capacitor should be placed underneath the IC to reduce the high-frequency components.

Supply current variable: 350 mA (estimated variable in 1 bit)

Supply voltage variable: 0.3 V

Noise pulse width: 10 ns (time in which fluctuation occurs)

C

= 350 mA × 4 bit/(0.3 V/10 ns)

∼− 47 nF

∼− 0.047 µF (when using a normal capacitor)

To control the fluctuation in the low-frequency components, it is recommended that the power supply on the

board be decoupled using a 10

µF to 50 µF capacitor.