Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

Preview PDF HTML

ST10F271B Datasheet(PDF) 169 Page - STMicroelectronics

Part # ST10F271B
Description  16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM
PDF  180 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F271B Datasheet(HTML) 169 Page - STMicroelectronics

Back Button ST10F271B Datasheet HTML 165Page - STMicroelectronics ST10F271B Datasheet HTML 166Page - STMicroelectronics ST10F271B Datasheet HTML 167Page - STMicroelectronics ST10F271B Datasheet HTML 168Page - STMicroelectronics ST10F271B Datasheet HTML 169Page - STMicroelectronics ST10F271B Datasheet HTML 170Page - STMicroelectronics ST10F271B Datasheet HTML 171Page - STMicroelectronics ST10F271B Datasheet HTML 172Page - STMicroelectronics ST10F271B Datasheet HTML 173Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 169 / 180 page
background image
ST10F271B/ST10F271E
Electrical characteristics
169/180
24.8.18
CLKOUT and READY
VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF
1.
These timings are given for characterization purposes only, in order to assure recognition at a specific
clock edge.
2.
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers
to the current bus cycle.
Table 79.
CLKOUT and READY timings
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
min.
max.
t29
CC
CLKOUT cycle time
25
25
2TCL
2TCL
ns
t30
CC
CLKOUT high time
9
–
TCL – 3.5
–
ns
t31
CC
CLKOUT low time
10
–
TCL – 2.5
–
ns
t32
CC
CLKOUT rise time
–
4
–
4
ns
t33
CC
CLKOUT fall time
–
4
–
4
ns
t34
CC
CLKOUT rising edge to
ALE falling edge
– 2 + tA
8 + tA
– 2 + tA
8 + tA
ns
t35
SR
Synchronous READY
setup time to CLKOUT
17
–
17
–
ns
t36
SR
Synchronous READY
hold time after CLKOUT
2–
2
–
ns
t37
SR
Asynchronous READY
low time
35
–
2TCL + 10
–
ns
t58
SR
Asynchronous READY
setup time 1
17
–
17
–
ns
t59
SR
Asynchronous READY
hold time 1
2–
2
–
ns
t60
SR
Async. READY hold time after
RD, WR high (Demultiplexed
Bus) 2
02tA + tC + tF
02tA + tC + tF
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com