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ST10F271B Datasheet(PDF) 171 Page - STMicroelectronics

Part # ST10F271B
Description  16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM
PDF  180 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F271B Datasheet(HTML) 171 Page - STMicroelectronics

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ST10F271B/ST10F271E
Electrical characteristics
171/180
24.8.19
External bus arbitration
V
DD = 5V
± 10%, V
SS = 0V, TA = -40 to +125°C, CL = 50pF
1.
Partially tested, guaranteed by design characterization.
Figure 59.
External bus arbitration (releasing the bus)
1.
The ST10F271 will complete the currently running bus cycle before granting bus access.
2.
This is the first possibility for BREQ to become active.
3.
The CS outputs will be resistive high (pull-up) after t64.
Table 80.
External bus arbitration timings
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
min.
max.
t61
SR
HOLD input setup time
to CLKOUT
18.5
–
18.5
–
ns
t62
CC
CLKOUT to HLDA high
or BREQ low delay
–
12.5
–
12.5
ns
t63
CC
CLKOUT to HLDA low
or BREQ high delay
–
12.5
–
12.5
ns
t64
CC
CSx release 1)
–
20
–
20
ns
t65
CC
CSx drive
– 415– 415
ns
t66
CC
Other signals release 1)
–
20
–
20
ns
t67
CC
Other signals drive
– 4
15
– 4
15
ns
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)



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