ST10F271B datasheet(174/180 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F271B/ST10F271E

174/180

Figure 61.

SSC master timing

The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

The bit timing is repeated for all bits to be transmitted or received.

Slave mode

VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

1st out bit

Last out bit

2nd out bit

2nd In bit

1st in bit

Last in bit

SCLK

MTSR

MRST

t308

t307

t308

t307

t305

t300

t301

t302

t304

t303

t306

t305

Table 82.

SSC slave mode timings

Symbol

Parameter

Max. Baudrate

6.6 MBd (1))

@FCPU = 40MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

min.

max.

min.

max.

t310

SR SSC clock cycle time(2)

150

8TCL

262144 TCL

t311

SR SSC clock high time

–

t310 / 2 – 12

–

t312

SR SSC clock low time

–

t310 / 2 – 12

–

t313

SR SSC clock rise time

–

t314

SR SSC clock fall time

–

t315

CC Write data valid after shift edge

–

2TCL + 30

t316

CC Write data hold after shift edge

–

t317p

Read data setup time before latch

edge, phase error detection on

(SSCPEN = 1)

–

4TCL + 12

–

t318p

Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

–

6TCL + 12

–

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