BMP388 datasheet(24/59 Pages) BOSCH

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Bosch Sensortec | BMP388 Datasheet

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Modifications reserved |Data subject to change without notice | Printed in Germany

Document number: BST-BMP388-DS001-07 Revision_1.7_112020

3.7.5.2.

FIFO full interrupt

FIFO Full interrupt status is asserted when the full interrupt condition is satisfied, when the filling level of the FIFO

number of unread bytes in the FIFO = fifo_length_1 & fifo_length_0 is equal or higher than 504.

The status of the FIFO full interrupt can be read back through the ffull_int bit. Interrupt status is cleared by reading the ffull_int

bit high ‘1’ when the FIFO filling level is lower than 504.

The FIFO full interrupt is propagated to INT pad only when it is enabled by setting bit ffull_en=‘1’. Latching mode configuration

bit int_latch selects whether the interrupt status or condition is propagated to the INT pad.

Figure 9:FIFO full interrupt, non-latched, with reads from FIFO

Figure 10: FIFO full interrupt, latched, with reads from FIFO

3.7.5.3.

Data ready

Data ready interrupt status int_status.drdy is asserted after a pressure and temperature measurement ends and conversion

results are stored to the data registers and to the FIFO. The status of the interrupt can be read back through the drdy bit.

The data ready interrupt is propagated to INT pad when it is enabled by setting drdy_en=‘1’. Interrupt status is cleared by

reading drdy bit high ‘1’. Data ready INT pad contribution is cleared automatically 2.5 ms after the interrupt assertion in the

non-latched mode (int_latch=’0’).

Corner cases:

•

If data ready interrupt is changed from latched to non-latched mode (int_latched changed from ‘1’ to ‘0’) after the

interrupt was already asserted;

timer is not running and it is not starting during the ongoing measurement, self-clearing does not happen. Timer is

starting when next data ready comes.

•

If data ready is changed to be propagated to INT pad (drdy_int changed from ‘0’ to ‘1’) after the interrupt was

already asserted;

data ready INT pad contribution remains ‘0’ until next data ready interrupt assertion.

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