Typical applications

STi5202

4/9

1.1

Detailed features

The STi5202 is a single-chip,standard-definition video decoder including:

●

Flexible audio decoder

●

●

●

●

Transport filtering and descrambling

●

SVP compliant

●

Graphics engine and dual display: standard and enhanced definition

The STi5202 also features the following embedded interfaces:

●

USB 2.0 host controller/PHY interface

●

DVI/HDMI™ output (optional)

●

Low-cost modem

●

100BT ethernet controller with integrated MAC and MII/RMII interface for external PHY

The processor subsystem uses the ST40 32-bit superscaler RISC CPU and includes:

●

266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU

●

5-stage pipeline, delayed branch support

●

Floating point unit, matrix operation support

●

Debug port, interrupt controller

The transport subsystem includes:

●

TS merger/router

–

Merging of 3 external transport streams (2 serial/parallel inputs, 1 bidirectional

interface)

–

Transport streams from memory support

–

NRSS-A module interface

●

Programmable transport interfaces (PTIs)

–

Two programmable transport interfaces

–

Two transport stream demultiplexers: DVB, DIRECTV®, ATSC, ARIB, OpenCable,

DCII

–

Integrated DES, AES, DVB and Multi2 descramblers

–

NDS random access scrambled stream protocol (RASP) compliant

–

NDS ICAM CA

–

Support for VGS, Passage