VS1103B datasheet(19/61 Pages) ETC2

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VLSI

Solution

VS1103b

VS1103B

5. SPI BUSES

After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the

WRITE sequence.

After the last bit has been sent, DREQ is driven low for the duration of the register update, marked

“execution” in the ﬁgure. The time varies depending on the register and its contents (see table in Chap-

ter 6.6 for details). If the maximum time is longer than what it takes from the microcontroller to feed

the next SCI command or SDI byte, status of DREQ must be checked before ﬁnishing the next SCI/SDI

operation.

5.5.4 SCI Multiple Write

10 11 12 13 14 15 16 17

address

XCS

SCK

15 14

instruction (write)

DREQ

0 X

execution

15 14

data out 1

data out 2

execution

32 33

d.out n

m−2m−1

Figure 7: SCI Multiple Word Write

VS1103b allows for the user to send multiple words to the same SCI register, which allows fast SCI

uploads, shown in Figure 7. The main difference with a single write is that instead of bringing XCS up

after sending the last bit of a data word, the next data word is sent immediately. After the last data word,

XCS is driven high as with a single word write.

After the last bit of a word has been sent, DREQ is driven low for the duration of the register update,

marked “execution” in the ﬁgure. The time varies depending on the register and its contents (see table

in Chapter 6.6 for details). If the maximum time is longer than what it takes from the microcontroller

to feed the next SCI command or SDI byte, status of DREQ must be checked before ﬁnishing the next

SCI/SDI operation.

Version 1.01, 2007-09-03

VS1103B Datasheet(PDF) 19 Page - List of Unclassifed Manufacturers