Glitch-Free Digital Step Attenuator

3

Jul 12, 2021

F1950 SPECIFICATION (31.75 dB Range)

Specifications apply at VDD = +3.3V, fRF = 2000MHz, and TC= +25°C, EVkit losses are de-embedded (see p. 17) for spec purposes

Parameter

Comment

Sym.

Min

Typical

Max

Units

Logic Input High

CLK, LE, DATA, D[6:0], VMODE

VIH

2.3

3.6

V

Logic Input Low

CLK, LE, DATA, D[6:0], VMODE

VIL

0.7

V

Logic Current

VMODE

IIH, IIL

-5

+5

μA

Supply Voltage(s)

Main Supply

VDD

3.0

3.30

5.25

V

Supply Current

Total

IDD

0.25

0.51

mA

Temperature Range

Operating Range (Case)

TC

-40

+100

°C

Frequency Range

Operating Range

FRF

150

5000

MHz

RF1, RF2 Return Loss

dB(s11), dB(s22)

S11, S22

-22

dB

Minimum Attenuation

D[6:0] = [0000000]

AMIN or

IL

1.3

1.9

dB

Maximum Attenuation

D[6:0] = [1111111]

AMAX

32.6

33.0

dB

Minimum Gain Step

Least Significant Bit

LSB

0.25

dB

Phase Delta

Phase change AMIN vs. AMAX

ΦΔ

34

deg

Differential Non-Linearity

Max error between

adjacent steps

DNL

0.10

dB

Integral Non-Linearity

Max Error vs. line (AMIN ref) to

13.75 dB ATTN

INL1

0.02

0.30

dB

Integral Non-Linearity

Max Error vs. line (AMIN ref) to

31.75 dB ATTN

INL2

0.27

0.45

dB

Input IP3

D[6:0] = [0000000] = AMIN

D[6:0] = [0111111] = A15.75

D[6:0] = [1111111] = AMAX

 P

IN = +10 dBm per tone

 50 MHz Tone Separation

IP3I1

IP3I2

IP3I3

+602

+59

+57

+63

+61

+61

dBm

0.1 dB Compression

Please note ABS MAX

Input power on Page 2

 D[6:0] = [0001010] = A

2.5

 Baseline P

IN

= 20 dBm

P0.1

27.5

dBm

Settling Time

 Start LE rising edge > V

IH

 End +/-0.10 dB Pout settling

 15.75 – 16.00 transition

TLSB

400

ns

Serial Clock Speed

SPI 3 wire bus

FCLK

20

50

MHz

Parallel to Serial Setup

SPI 3 wire bus

A

100

ns

Serial Data Hold Time

SPI 3 wire bus

B

10

ns

LE delay from final

serial clock rising edge

SPI 3 wire bus

C

10

ns

SPECIFICATION NOTES:

1

– Items in min/max columns in bold italics are Guaranteed by Test

2

– All other Items in min/max columns are Guaranteed by Design Characterization