SCKO0

150 ns

SCKO1

SCKO2

SCKO3

FS2, 1

Stable

Clock T ransition Region

Stable

33.8688 MHz

SR

CSEL

50 ns

Reset

Reset Removal

1024 Master Clocks

VDD

2.4 V

2.0 V

1.6 V

Internal Reset

Master Clock

PLL1707-Q1

www.ti.com

SLES259A

– JUNE 2010 – REVISED MARCH 2011

Table 4. Sampling Frequencies and System Clock Output Frequencies

SAMPLING

SAMPLING RATE

256 fS SCKO2 (MHZ)

384 fS SCKO3 (MHZ)

FREQUENCY (kHz)

32

Standard

8.192

12.288

44.1

Standard

11.2896

16.9344

48

Standard

12.288

18.432

64

Double

16.384

24.576

88.2

Double

22.5792

33.8688

96

Double

24.576

36.864

Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time

from sampling frequency change to SCKO settling is 300 ns maximum.

The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 10 illustrates

SCKO transient timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External

buffers are recommended on all output clocks in order to avoid degrading the jitter performance of the PLL1707.

Figure 10. SCKO Transient Timing

Power-On Reset

The PLL1707 has an internal power-on reset circuit. Throughout the reset period, all clock outputs are enabled

with the default settings after power-up time. Initialization by internal power-on reset is done automatically during

1024 master clocks at VDD > 2.0 V (TYP). Power-on reset timing is shown in Figure 11.

Figure 11. Power-On Reset Timing

Copyright

© 2010–2011, Texas Instruments Incorporated

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