ST10F271Z1 datasheet(152/185 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F271Z1

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Figure 48.

Generation mechanisms for the CPU clock

25.8.3

Clock generation modes

Next Table 69 associates the combinations of these three bits with the respective clock

generation mode.

The external clock input range refers to a CPU clock range of 1...64 MHz. Besides, the PLL usage is limited

to 4-8 MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the

internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced through an external

clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can

be used).

The maximum depends on the duty cycle of the external clock signal: when 64 MHz is used, 50% duty

cycle shall be granted (low phase = high phase = 7.8 ns); when 32 MHz is selected a 25% duty cycle can

be accepted (minimum phase, high or low, again equal to 7.8 ns).

The limits on input frequency are 4-8 MHz since the usage of the internal oscillator amplifier is required.

Also when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator

shall be used: it is not possible to force any clock though an external clock source.

TCLTCL

fCPU

fXTAL

fCPU

fXTAL

Phase Locked Loop operation

Direct clock drive

TCL

fCPU

fXTAL

Prescaler operation

Table 69.

On-chip clock generator selections

P0.15-13

(P0H.7-5)

CPU frequency

fCPU = fXTAL x F

External clock

input range 1) 3)

Notes

FXTAL x 4

4 to 8MHz

Default configuration

FXTAL x 3

5.3 to 8MHz

See Table 70

FXTAL x 8

4 to 8MHz

FXTAL x 5

6.4 to 8MHz

FXTAL x 1

1 to 64MHz

Direct drive (oscillator bypassed)

FXTAL x 10

4 to 6.4MHz

FXTAL / 2

4 to 8MHz

CPU clock via prescaler 3)

FXTAL x 16

4MHz

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