STA333W datasheet(27/50 Pages) STMICROELECTRONICS

27 / 50 page

DocID13365 Rev 3

27/50

STA333W

Channel input mapping

Each channel received via I²S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I²S input channel to its corresponding processing channel.

6.1.3

Configuration register C (addr 0x02)

DDX power output mode

DDX compensation pulse size register

Table 20. Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

0C1IM

0: processing channel 1 receives left I²S input

1: processing channel 1 receives right I²S input

7R/W

0C2IM

0: processing channel 2 receives left I²S input

1: processing channel 2 receives right I²S input

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

001

011

Table 21. DDX power output mode

Bit

R/W

RST

Name

Description

R/W

OM0

The DDX power output mode selects the configuration

of the DDX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

1R/W

1OM1

Table 22. DDX compensating pulse size

Bit

R/W

RST

Name

Description

R/W

CSZ0

When OM[1:0] = 11, this register determines the size of

the DDX compensating pulse from 0 to 15 clock periods:

0000: 0 ns (0 ticks) compensating pulse size

0001: 20 ns (1 tick) clock period compensating pulse

size

.....

1111: 300 ns (15 ticks) clock period compensating pulse

size

3R/W

0CSZ1

4R/W

1CSZ2

5R/W

0CSZ3

STA333W Datasheet(PDF) 27 Page - STMicroelectronics

STA333W Datasheet(HTML) 27 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL