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STA339BWS Datasheet(PDF) 39 Page - STMicroelectronics |
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STA339BWS Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 79 page ![]() DocID015276 Rev 9 39/79 STA339BWS Register description 79 2.0 channels, two full-bridges (OCFG = 00) Mapping: FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B FFX4A -> OUT4A FFX4B -> OUT4B Default modulation: FFX1A/1B configured as ternary FFX2A/2B configured as ternary FFX3A/3B configured as lineout ternary FFX4A/4B configured as lineout ternary On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, volume control or EQ have no effect on channels 3 and 4. In this configuration the PWM slot phase is the following as shown in Figure 16. Figure 16. 2.0 channels (OCFG = 00) PWM slots OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B |
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