| Electronic Components Datasheet Search |
|
L5963 Datasheet(PDF) 19 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L5963 Datasheet(HTML) 19 Page - STMicroelectronics |
|
19 / 49 page ![]() DocID028553 Rev 3 19/49 L5963 Functional Description 48 6 Functional Description 6.1 Operative modes L5963 has three main operative modes: Shutdown mode: all enable pins are low and the device is completely off. In this condition the quiescent current is typically 1.5 μA. Standby mode: the linear regulator is configured as stand-by regulator by connecting ENLDO directly to VINLDO. In this condition the quiescent current is typically 25 μA. Normal mode: the linear regulator works as LDO and/or other blocks (DC/DC or HSD) are turned on. 6.2 Blocks functional description 6.2.1 Unregulated supply input voltage (VINLDO) This terminal provides the power for internal circuitry to bias band-gap reference, standby regulator and other circuitry in the device. If backup function is needed, an external capacitor connected to this pin shall be charged through an external diode which is used to block reverse discharging. With backup function, when the system battery is removed or drops too low suddenly, the internal bias and regulator can operate correctly for a certain time, which avoids MCU to work abnormally and allows MCU to have enough time to turn-off. 6.2.2 Low voltage warning monitor (related pins: VDIN, VDOUT, VDDLY) An external voltage can be sensed through the VDIN pin. This voltage is scaled using an external resistor network and compared with an internal threshold to detect a low voltage condition (Figure 9.). Once the input voltage is below the threshold, the low voltage warning output terminal (VDOUT) is pulled low after the designed glitch-filtering (~12 μs). VDOUT is an open drain output. If the input returns above the threshold with the specified hysteresis, VDOUT is released after a defined delay, determined by the capacitor on pin VDDLY. The threshold is fixed to 0.95 V typ. The capacitor on VDDLY pin sets VDOUT delay. A current source (~9 μA) on this pin charges the external capacitor to generate the required delay, programmable by adjusting the value of the capacitor. This voltage monitor can also be used to monitor DC/DC2 output. Changing the ratio of the external resistor divider the low voltage warning threshold can be adjusted. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |