L5963DN-EHT datasheet(20/49 Pages) STMICROELECTRONICS

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Functional Description

L5963

20/49

DocID028553 Rev 3

Figure 9. Low voltage warning monitor & delay schematic

6.2.3

Power-good reset (related pins: LDOOK, LDOOKDLY)

LDOOK monitors the regulator output VOUTLDO. Its circuit topology is the same as the

voltage detector one (Figure 9). Its threshold is fixed to 95% typ of the feedback voltage,

and the hysteresis is always ~2% typ. Pin LDOOK is an open drain output, and pin

LDOOKDLY is used to adjust the delay in the release of LDOOK output.

6.2.4

Power-good function of DC/DC1 (related pins: SW1OK, SW1OKDLY)

SW1OK monitors DC/DC1 output. Its circuit topology is the same as the voltage detector

one (Figure 9). Its threshold can't be adjusted, it is always 95% typ of the feedback voltage,

and the hysteresis is ~35mV typ. Pin SW1OK is an open drain output, and pin SW1OKDLY

is used to adjust its delay.

6.2.5

Over voltage shutdown

Two internal over voltage shutdown (OV) blocks are included in L5963. One (OV1) senses

VBAT pin, the other (OV2) detects VINLDO pin.

If VBAT gets too high, to prevent any damage, DC/DC1, DC/DC2 and the high-side driver

are disabled by OV1. They will be turned on once VBAT returns below the detection

threshold with the specified hysteresis.

If the linear regulator works as a non-standby regulator and VINLDO gets too high, to

prevent any damage the LDO is disabled by OV2. It is turned on once VINLDO returns

below the detection threshold with the specified hysteresis.

On the contrary, the linear regulator works as a standby regulator, OV2 doesn't intervene

and the regulator continues to work even if VINLDO increases.

L5963DN-EHT Datasheet(PDF) 20 Page - STMicroelectronics