STPM32TR datasheet(49/89 Pages) STMICROELECTRONICS

49 / 89 page

Examples

All frames in the following examples do not contain CRC byte, which has to be added just in case the feature has

not been disabled previously. After that CRC has been disabled, the frame consists of four bytes only.

To write bits from 31 to 16 (most significant bits) in row 1 with data byte 0xABCD and read row 2 in the following

transaction, the first four bytes of the transmission (without CRC) are: 04_03_CD_AB. To receive data from

To write lower (least significant) 16-bits in row 3 with data #AABB and read back from the same row the frame to

send is 06_06_BB_AA, followed by the frame FF_FF_FF_FF to receive requested data from the device.

The sent frame changes according to LSBfirst setting:

Table 25. LSBfirst example

LSBfirst = 0

04_03_CD_AB

LSBfirst = 1

20_C0_B3_D5

MISO line is valid as well. In this case, there is a full-reverse data transmission when LSBfirst = 1,since data bit

reception order changes as shown in Table 26.

Table 26. LSBfirst and MISO line

Byte[0]

Byte[1]

Byte[2]

Byte[3]

LSBfirst = 0

[7:0]

[15:8]

[23:16]

[31:24]

LSBfirst = 1

[0:7]

[8:15]

[16:23]

[24:31]

LSBfirst can be programmed using the transactions (other configuration bits involved in the transaction are set to

their default states):

Table 27. LSBfirst programming

LSBfirst = 1

24_24_07_CO

LSBfirst = 0

24_24_EO_02

The transaction to write LSBfirst = 0 is byte-reversed, since the system has moved from the LSBfirst = 1

condition. The read address is set so to read in the following transaction the content of US_REG1.

Following the frames to enable/disable CRC feature:

Table 28. CRCenable programming

CRCenable = 1

24_24_07_40

CRCenable = 0

24_24_07_00

To reset all SPI and UART status register's bits, the following frame should be sent: 28_29_00_00.

To clear SPI status bits only, SPI-master can send 1 s sequence to UART status bit register. Referring to the

previous example, this leads to the following transaction: 28_29_FF_00.

Events are associated to interrupts so that, when the correspondent event mask bit in SPI IRQ register is

activated, INT line is sensitive to that event.

For example, to activate CRC error interrupt (bit 12, related to status bit 28), the mask 0x1000 has to be written to

write address 0x28 by the following transaction: 28_28_00_10.

STPM32, STPM33, STPM34

Communication protocol

DS10272 - Rev 13

page 49/89

STPM32TR Datasheet(PDF) 49 Page - STMicroelectronics

STPM32TR Datasheet(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datasheet Download

Link URL