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1.10.3 Datafield #1

Figure 9.

Datafield #1 contains either the lower 8 bits of a 12-Bit frame or the complete byte of an 8-Bit transfer.

Note, that SOUT is always showing the content of the register currently accessed and not a copy of SIN as dur-

ing the Address/ Command field.

1.10.4 Datafield #2 /CRC

Figure 10.

Datafield #2 contains either the upper four bits of a 12-Bit frame or zeros in case of an 8-Bit transfer. This field

is followed by a four bit CRC sequence that is calculated based upon the polynom 0x11h (17 decimal). This

sequence is simply the remainder of a polynomial division performed on the data previously transferred. If the

CRC appended to the SIN sequence fails, any writing will be disabled and an error is signalled via NINT. Another

remainder is calculated on the SOUT stream and appended accordingly to allow the application software to val-

idate the correctness of incoming data. To aid evaluation, the CRC checking can be turned off by writing arbi-

trary data with a valid CRC to address 15. CRC-checking will be reenabled upon another operation of this kind

(Toggled information).

D7

D6

D5

D4

D3

D2

D1

D0

SIN: Data to write

SOUT: Data currently in selected register

Lower 8 Bit of 12 Bit data

99AT0017

D11

D10

D9

D8

CRC3

CRC2

CRC1

CRC0

SIN: Data to write

SOUT: Data currently in selected register

Upper 4 Bit of 12 Bit data (Zero if 8 Bit data)

CRC Check sequence

to be appended to tranferred data

Note that upon CRC check failure

no write operation will be performed

SIN: CRC of SIN sequence

SOUT: CRC of SOUT sequence

99AT0018