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AD4083BBCZ Datasheet(PDF) 1 Page - Analog Devices |
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AD4083BBCZ Datasheet(HTML) 1 Page - Analog Devices |
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1 / 94 page  Data Sheet AD4083 16-Bit, 40MSPS, Low Noise, Low Power SAR ADC Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT One Analog Way, Wilmington, MA 01887-2356, U.S.A. | Tel: 781.935.5565 | ©2026 Analog Devices, Inc. All rights reserved. FEATURES ► 16-bit resolution, no missing codes ► Throughput: 40MSPS, 48.43ns conversion latency ► Noise spectral density: 10.69nV/√Hz,165.9dBFS/Hz ► Low 1/f, low frequency noise (0.1Hz to 10Hz): 265nV rms ► Low Power:70.2mW typical at 40MSPS ► INL: ±8ppm (typ), ±12ppm (max) ► Dynamic range: 92.94dBFS ► SNR/THD ► 92.2dB (typ)/−111dB (typ) at fIN = 1kHz ► 92dB (typ)/−103.4dB (typ) at fIN = 1MHz ► Easy Drive ► 6V p-p differential input range ► Continuous signal acquisition ► Linearized, 5μA/MSPS input current ► Integrated, low-drift reference buffer and decoupling ► Integrated VCM generation ► Digital features and data interface ► Conversion result FIFO, 16K sample depth ► Digital averaging filter with up to 210 decimation ► SPI configuration ► Configurable data interface ► Single lane, DDR, serial LVDS, 640Mbps per lane ► Dual lane, DDR, serial LVDS, 320Mbps per lane ► Single/quad lane SPI data interface ► Package ► 49-ball, 5mm × 5mm CSP_BGA, 0.65mm pitch ► Integrated supply decoupling capacitors ► Operating temperature range: −40°C to +85°C APPLICATIONS ► Digital imaging ► Cell analysis ► Spectroscopy ► Automated test equipment ► High speed data acquisition ► Digital control loops, hardware in the loop ► Power quality analysis ► Source measurement units ► Electron and X-ray microscopy ► Radar level measurement ► Nondestructive test FUNCTIONAL BLOCK DIAGRAM Figure 1. AD4083 Functional Block Diagram GENERAL DESCRIPTION The AD4083 is a high speed, low noise, low distortion, 16-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > 90dBFS) at signal frequencies in excess of 1MHz enables the AD4083 to service a wide variety of precision, wide bandwidth data acquisition applications. Simplification of the input anti-alias filter design can be accomplished by applying over- sampling along with the integrated digital filtering and decimation to reduce noise and lower the output data rate for applications that do not require the lowest latency of the AD4083. The AD4083 Easy Drive features reduce both signal chain com- plexity and power consumption while enabling greater channel density and flexibility in companion component selection. The prod- uct input structure was designed to minimize any input dependent signal currents, therefore reducing any converter induced settling artifacts. The continuous acquisition architecture allows settling across the entire conversion cycle, easing ADC driver settling and bandwidth requirements as compared to other high-speed data converters. The AD4083 includes several elements that simplify data converter integration: a low drift reference buffer, low dropout (LDO) regula- tors to generate ADC core and digital interface supply rails, and a 16K result data first-in first out (FIFO) that can greatly reduce the load on the digital host. Additionally, critical supply and reference decoupling capacitors are integrated in the package to ensure optimum performance, simplify printed circuit board (PCB) layout, and reduce the overall solution footprint. |
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