F320C3BD datasheet(21/68 Pages) INTEL

21 / 68 page

Intel£ Advanced+ Boot Block Flash Memory (C3)

Datasheet

The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs

last) which prevents possible bus errors that might occur if Status Register contents change while

being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register

will not indicate completion of a Program or Erase operation.

When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits in the

status register indicate whether the WSM was successful in performing the preferred operation (see

Table 9, “Status Register Bit Definition” on page 26).

4.1.4.1

Clear Status Register

The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7; but, the WSM

cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error

conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By

allowing the system software to control the resetting of these bits, several operations may be

performed (such as cumulatively programming several addresses or erasing multiple blocks in

sequence) before reading the status register to determine if an error occurred during that series.

Clear the status register before beginning another command or sequence. The Read Array

command must be issued before data can be read from the memory array. Resetting the device also

clears the Status Register.

4.2

Program Mode

Programming is executed using a two-write cycle sequence. The Program Setup command (0x40)

is issued to the CUI followed by a second write which specifies the address and data to be

programmed. The WSM will execute a sequence of internally timed events to program preferred

bits of the addressed location, then verify the bits are sufficiently programmed. Programming the

memory results in specific bits within an address location being changed to a “0.” If users attempt

to program “1”s, the memory cell contents do not change and no error occurs.

The Status Register indicates programming status. While the program sequence executes, status bit

7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the

only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the program-status bits should be checked. If the programming

operation was unsuccessful, bit SR[4] of the Status Register is set to indicate a program failure. If

SR[3] is set, then VPP was not within acceptable limits, and the WSM did not execute the program

command. If SR[1] is set, a program operation was attempted on a locked block and the operation

was aborted.

The status register should be cleared before attempting the next operation. Any CUI instruction can

follow after programming is completed; however, to prevent inadvertent status-register reads, be

sure to reset the CUI to read-array mode.

4.2.1

12-Volt Production Programming

When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC

pin. Note that if VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above

1.65 V to perform in-system flash modifications. When VPP is connected to a 12 V power supply,

the device draws program and erase current directly from the VPP pin. This eliminates the need for

an external switching transistor to control VPP. Figure 7 on page 31 shows examples of how the

flash power supplies can be configured for various usage models.

F320C3BD Datasheet(PDF) 21 Page - Intel Corporation

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