W144
Document #: 38-07153 Rev. *B
Page 13 of 14
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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Package Drawing and Dimension
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Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as defined by Philips. All product and company names
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fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
––3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
–40
–
Ω
Ordering Information
Ordering Code
Package Type
W144H
48-Pin SSOP (300-mil)
W144HT
48-Pin SSOP (300-mil) – Tape and Reel
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz (continued)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100.2 MHz
Unit
Min.
Typ.
Max.
48-Lead Shrunk Small Outline Package O48
51-85061-*C
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