M14C32 datasheet(5/14 Pages) STMICROELECTRONICS

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M14C64, M14C32

Figure 6. Write Mode Sequences with WC=1

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01120B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

the seven bits are fixed at 1010000b (A0h), as

shown in Table 5.

The 8th bit is the read or write bit (RW). This bit is

set to ‘1’ for read and ‘0’ for write operations. If a

match occurs on the Device Select Code, the cor-

responding memory gives an acknowledgment on

the SDA bus during the 9th bit time. If the memory

does not match the Device Select code, it will de-

select itself from the bus, and go into stand-by

mode.

Each data byte in the memory has a 16-bit (two

byte wide) address. The Most Significant Byte (Ta-

ble 3) is sent first, followed by the Least significant

Byte (Table 4). Bits b15 to b0 form the address of

the byte in memory. Bits b15 to b13 are treated as

a Don’t Care bit on the M14C64 memory. Bits b15

to b12 are treated as Don’t Care bits on the

M14C32 memory.

Write Operations

Following a START condition the master sends a

Device Select code with the RW bit set to ’0’, as

shown in Table 6. The memory acknowledges it

and waits for two bytes of address, which provides

access to the memory area. After receipt of each

byte address, the memory again responds with an

acknowledge and waits for the data byte. Writing

in the memory may be inhibited if input pin WC is

taken high.

Any write command with WC=1 (during a period of

time from the START condition until the end of the

two bytes address) will not modify the memory

content and will NOT be acknowledged on data

bytes, as shown in Figure 6.

Byte Write

In the Byte Write mode, after the Device Select

code and the address, the master sends one data

byte. If the addressed location is write protected by

the WC pin, the memory replies with a NoACK,

and the location is not modified. If, instead, the WC

pin has been held at 0, as shown in Figure 7, the

memory replies with an ACK. The master termi-

nates the transfer by generating a STOP condi-

tion.

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