| Electronic Components Datasheet Search |
|
M28F201 Datasheet(PDF) 16 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
M28F201 Datasheet(HTML) 16 Page - STMicroelectronics |
|
16 / 21 page ![]() PRESTO F ERASE ALGORITHM The PRESTO F Erase Algorithm guarantees that the device will be erased in a reliable way. The algorithm first programs all bytes to 00h in order to ensure uniform erasure. The programming follows the PRESTO F Programming Algorithm. Erase is set-up by writing 20h to the command register, the erasure is started by repeating this write cycle. Erase Verify is set-up by writing A0h to the com- mand register together with the address of the byte to be verified. The subsequent read cycle reads the data which is compared to FFh. Erase Verify begins at address 0000h and continues to the last address or until the comparison of the data to FFh fails. If this occurs, the address of the last byte checked is stored and a new Erase operation performed. Erase Verify then continues from the address of the stored location. PRESTO F PROGRAM ALGORITHM The PRESTO F Programming Algorithm applies a series of 10 µs programming pulses to a byte until a correct verify occurs. Up to 25 programming operations are allowed for one byte. Program is set-up by writing 40h to the command register, the programming is started after the next write cycle which also latches the address and data to be programmed. Program Verify is set-up by writing C0h to the command register, followed by a read cycle and a compare of the data read to the data expected. During Program and Program Verify op- erations a MARGIN MODE circuit is activated to guarantee that the cell is programmed with a safety margin. PROGRAM ALL BYTES TO 00h AI00649 n=0, Addr=00000h Last Addr ERASE SET-UP Wait 10ms ERASE VERIFY Latch Addr. READ DATA OUTPUT Data OK Wait 6 µs ++n = Addr++ READ COMMAND VPP = 12V VPP < 6.5V FAIL VPP < 6.5V, PASS YES NO YES NO YES NO 1000 Figure 12. Erasing Flowchart AI00677 n= 0 Last Addr PROGRAM VERIFY Wait 10 µs PROGRAM SET-UP Latch Addr, Data READ DATA OUTPUT Data OK Wait 6 µs ++n =25 Addr++ READ COMMAND VPP = 12V VPP < 6.5V FAIL VPP < 6.5V, PASS YES NO YES NO YES NO Figure 13. Programming Flowchart 16/21 M28F201 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |