No tes : 1. About mask bits Mi0 to Mi7 a logic ”0” level means disabling condition, a logic ”1” level means enabling condition.

2. A null mask or a RESET pulse clear the mask and the deep background mask registers and disable channel 0 extraction function.

3. Reading of OR2 is optional after mask store or redefinition, because function is activated only by not-null mask writing.

4. After mask store (N2 N1 N0) is the sum of activated channels, after DR is the sum of active channels ; Tn = 1/0 means activation/sup-

pression of the function after store while after DR only Tn = 1 can appear to tell a not-null configuration to be extracted.

5. Reading of OR2 is imperative after DR in order to step the data transfer ; reading of OR1 is also needed to scan in descending order

the priority register. Relevant messages only are considered, that means only messages with a MSD label different from 0 1.

6. (P2 P1 P0) is the PCM bus on which the message copied in OR1 was found ; Fn is a continuation bit telling respectively on level 1/0

for any more/no more extraction step to be performed.

INSTRUCTION5: TRANSFER OF AN OUTPUT CHANNEL CONTROL WORD

Control Signals

Data Bus

Notes

Match C/D

CS

WR

RD

D7

D6

D5

D4

D3

D2

D1

D0

X

0

0

0

1

X

X

X

X

X

Bo2 Bo1 Bo0 1

X

0

0

0

1

X

X

X

Co4 Co3 Co2 Co1 Co0 2

Yes

1

0

0

1

X

X

X

X

1

0

0

0

Instruction Opcode

Yes

0

0

1

0

C7

C6

C5

C4

C3

C2

C1

C0

OR1: CM selected CM word copy.

Yes

10

10

A7

(Bo2

A6

Bo1

A5

Bo0

C8

C8

1

1

0

0

0

0

0

0)

OR2: that is.

INSTRUCTION6: CHANNEL 0 SELECTION MASK STORE/DATA TRANSFER

Control Signals

Data Bus

Notes

Match C/D

CS

WR

RD

D7

D6

D5

D4

D3

D2

D1

D0

X

0

0

0

1

X

X

X

X

X

Mi7

Mi6

Mi5

1

selection mask.

X

0

0

0

1

X

X

X

Mi4

Mi3

Mi2

Mi1

Mi0

2

selection mask.

Yes

1

0

0

1

X

X

X

X

1

1

1

0

Instruction Opcode

Mask store control

Yes

0

0

1

0

(previous content)

OR1: register is not affected.

Yes

1

0

1

0

N2

N1

N0

Tn

1

1

1

0

OR2: see below.

First Data Transfer (after DR going low)

Yes

0

0

1

0

(previous content)

OR1: register is not affected.

Yes

1

0

1

0

N2

N1

N0

Tn

1

1

1

0

OR2: see below.

Repeated Data Transfer (after first OR2 transfer)

Yes

0

0

1

0

S7

S6

S5

S4

S3

S2

S1

S0

OR1: expected message stored in SM.

Yes

1

0

1

0

P2

P1

P0

Fn

1

1

1

0

OR2: see below.

M3488 WITH LESS PCM LINKS THAN 32

CHANNELS

It is also possible to use M3488 when the PCM

frames are made up of a number of channels other

than 32.

Suppose that the PCM frames are made up of N-

Channels, which will be numbered from 0 to (N-1).

Each PCM frame will thus be made up of a number

of bits multiplied by 8 ; this exactly equal to (N

Also, in this case, it is necessary to respect the tim-

ing relationshipbetween the different signals shown

on the data sheet ; in particular, a relation-ship is al-

ways carefully made between the rising edge of

SYNC and the first clock (CK) bit contained in the

slot time for bit 0 of channel 0.

In order to use M3488 with these frames, it is suffi-

cient, using the data bytes sent by the microproces-

sor, to modify the numbering of a few channels.

In particular :

a) in all instructions in which reference is made to the

input channel (N-1), the number 31 should be

substituted for the number (N-1) ;

b) in all instructions in which reference is made to the

output channel 0, the number N should be sub-

stituted for the number 0.

M3488

15/18