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M48T559Y Datasheet(PDF) 13 Page - STMicroelectronics |
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M48T559Y Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 18 page ![]() 13/18 M48T559Y BATTERY LOW WARNING The M48T559Y checks its battery voltage on pow- er-up. The BL (Battery Low) bit (D4 of 1FF0h) will be set on power-up if the battery voltage is less than 2.5V (typical). POWER-ON DEFAULTS Upon application of power to the device, the fol- lowing register bits are set to a ’0’ state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT. POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store en- ergy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic by- pass capacitor value of 0.1µF (as shown in Figure 14) is recommended in order to provide the need- ed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate neg- ative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These nega- tive spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to con- nect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Table 12. Reset AC Characteristics (TA = 0 to 70°C; VCC = 4.5V to 5.5V) Symbol Parameter Min Max Unit tR1 RSTIN1 Low to RST Low 50 200 ns tR2 RSTIN2 Low to RST Low 20 100 ms tR1HRZ RSTIN1 High to RST Hi-Z 40 200 ms tR2HRZ RSTIN2 High to RST Hi-Z 40 200 ms Figure 12. Reset Timing Waveforms AI01679 RSTIN1 RST RSTIN2 tR1 tR1HRZ Hi-Z tR2 tR2HRZ Hi-Z Figure 13. Supply Voltage Protection AI02169 VCC 0.1 µF DEVICE VCC VSS |
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