M58LW032 datasheet(16/61 Pages) STMICROELECTRONICS

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M58LW032A

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Burst Configuration Register

The Burst Configuration Register is used to config-

ure the type of bus access that the memory will

perform. The Burst Configuration Register bits are

described in Table 4. They specify the selection of

the burst length, burst type, burst X and Y laten-

cies and the Read operation. See figures 6 and 7

for examples of Synchronous Burst Read configu-

rations.

The Burst Configuration Register is set through

the Command Interface and will retain its informa-

tion until it is re-configured, the device is reset, or

the device goes into Reset/Power-Down mode.

The Burst Configuration Register is read using the

Read Electronic Signature Command at address

05h.

Read Select Bit (M15). The

Read

Select

bit,

M15, is used to switch between asynchronous and

synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set to

’1’ for asynchronous access.

X-Latency Bits (M13-M11). The X-Latency bits

are used during Synchronous Bus Read opera-

tions to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table 4,

Burst Configuration Register.

Internal Clock Divider Bit (M10). The

Internal

Clock Divider Bit is used to divide the internal clock

by two. When M10 is set to ‘1’ the internal clock is

divided by two, which effectively means that the X

and Y-Latency values are multiplied by two, that is

the number of clock cycles between the address

being latched and the first data becoming avail-

able will be twice the value set in M13-M11, and

the number of clock cycles between consecutive

reads will be twice the value set in M9. For exam-

ple 8-1-1-1 will become 16-2-2-2. When M10 is set

to ‘0’ the internal clock runs normally and the X

and Y-Latency values are those set in M13-M11

and M9.

Y-Latency Bit (M9). The Y-Latency bit is used

during Synchronous Bus Read operations to set

the number of clock cycles between consecutive

reads. The Y-Latency value depends on both the

X-Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each

clock cycle; when the Y-Latency is 2 the data

changes every second clock cycle. See Table 4,

Burst Configuration Register for valid combina-

tions of the Y-Latency, the X-Latency and the

Clock frequency.

Valid Data Ready Bit (M8). The

Valid

Data

Ready bit controls the timing of the Valid Data

Ready output pin, R. When the Valid Data Ready

bit is ’0’ the Valid Data Ready output pin is driven

Low for the active clock edge when invalid data is

output on the bus. When the Valid Data Ready bit

is ’1’ the Valid Data Ready output pin is driven Low

one clock cycle prior to invalid data being output

on the bus.

Burst Type Bit (M7). The Burst Type bit is used

to configure the sequence of addresses read as

sequential or interleaved. When the Burst Type bit

is ’0’ the memory outputs from interleaved ad-

dresses; when the Burst Type bit is ’1’ the memory

outputs from sequential addresses. See Tables 5,

Burst Type Definition, for the sequence of ad-

dresses output from a given starting address in

each mode.

Valid Clock Edge Bit (M6). The Valid Clock Edge

bit, M6, is used to configure the active edge of the

Clock, K, during Synchronous Burst Read opera-

tions. When the Valid Clock Edge bit is ’0’ the fall-

ing edge of the Clock is the active edge; when the

Valid Clock Edge bit is ’1’ the rising edge of the

Clock is active.

Burst Length Bit (M2-M0). The Burst Length bits

set the maximum number of Words that can be

output during a Synchronous Burst Read opera-

tion.

Table 4, Burst Configuration Register gives the

valid combinations of the Burst Length bits that the

memory accepts; Tables 5, Burst Type Definition,

give the sequence of addresses output from a giv-

en starting address for each length.

M5 M4 and M3 are reserved for future use.

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