33/37

M59DR008E, M59DR008F

Table 29. Ordering Information Scheme

Devices are shipped from the factory with the memory content erased (to FFFFh).

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 30. Revision History

Example:

M59DR008E

100 ZB

6

T

Device Type

M59

Architecture

D = Dual Bank Page Mode

Operating Voltage

R = 1.8V

Device Function

008E = 8 Mbit (512Kb x16), Dual Bank: 1/half-1/half partitioning, Top Boot

008F = 8 Mbit (512Kb x16), Dual Bank: 1/half-1/half partitioning, Bottom Boot

Random Speed

100 = 100 ns

120 = 120 ns

Package

N = TSOP48: 12 x 20mm

ZB = FBGA48: 0.75mm pitch

Temperature Range

1 = 0 to 70°C

6 = –40 to 85°C

Option

T = Tape & Reel packing

Date

Revision Details

September 1999

First Issue

10/06/99

FBGA Connections change (Table 1, Figure 2A)

10/20/99

FBGA Package Outline drawing and Mechanical Data change (Table 32, Figure 15)

Daisy Chain diagrams, Package and PCB Connections, added (Figure 16, 17)