M68Z128N datasheet(2/12 Pages) STMICROELECTRONICS

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M68Z128

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Figure 2. TSOP Connections

DQ0

A13

A10

DQ7

A11

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A15

A16

A12

VCC

A14

AI00657

M68Z128

VSS

Table 2. Absolute Maximum Ratings (1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Up to a maximum operating VCC of 5.5V only.

3. One output at a time, not to exceed 1 second duration.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

0 to 70

°C

TSTG

Storage Temperature

–65 to 150

°C

VIO

(2)

Input or Output Voltage

–0.3 to VCC + 0.3

VCC

Supply Voltage

–0.3 to 7.0

(3)

Output Current

Power Dissipation

This device has an automatic power-down feature,

reducing the power consumption by over 99%

when deselected.

The M68Z128 is available in TSOP32 (8 x 20mm)

package.

READ MODE

The M68Z128 is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and both Chip Enables (E1 and E2) are as-

serted. This provides access to data from eight of

the 1,048,576 locations in the static memory array,

specified by the 17 address inputs. Valid data will

be available at the eight output pins within tAVQV

after the last stable address, providing G is Low,

E1 is Low and E2 is High. If Chip Enable or Output

Enable access times are not met, data access will

be measured from the limiting parameter (tE1LQV,

tE2HQV, or tGLQV) rather than the address. Data out

may be indeterminate at tE1LQX, tE2HQX and tGLQX,

but data lines will always be valid at tAVQV.

WRITE MODE

The M68Z128 is in the Write mode whenever the

W and E1 pins are Low, with E2 High. Either the

Chip Enable inputs (E1 and E2) or the Write En-

able input (W) must be de-asserted during Ad-

dress transitions for subsequent write cycles.

Write begins with the concurrence of both Chip

Enables being active with W low. Therefore, ad-

dress setup time is referenced to Write Enable and

both Chip Enables as tAVWL, tAVE1L and tAVE2H re-

spectively, and is determined by the latter occur-

ring edge.

The Write cycle can be terminated by the earlier

rising edge of E1, W, or the falling edge of E2.

If the Output is enabled (E1 = Low, E2 = High and

G = Low), then W will return the outputs to high im-

pedance within tWLQZ of its falling edge. Care must

be taken to avoid bus contention in this type of op-

eration. Data input must be valid for tDVWH before

the rising edge of Write Enable, or for tDVE1H be-

fore the rising edge of E1 or for tDVE2L before the

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