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AS3953A-BDFM Datasheet(PDF) 42 Page - ams-OSRAM AG |
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AS3953A-BDFM Datasheet(HTML) 42 Page - ams-OSRAM AG |
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42 / 71 page  ams Datasheet Page 41 [v1-05] 2019-Feb-15 Document Feedback AS3953A − Detailed Description SPI Timing Figure 49: Timing Parameters Symbol Parameter Min Typ Max Units Note General Timing (VDD = VDD_IO = VDD_D = 3.3V, Temperature 25°C) TSCLK SCLK period 200 ns TSCLK=TSCLKL+TSCLKH, during EEPROM read the SCLK period has to be increased to 1μs (this limitation is imposed by EEPROM read access time) TSCLKL SCLK low 80 ns TSCLKH SCLK high 80 ns TSSH SPI reset (/SS high) 50 ns TNCSL /SS falling to SCLK rising 25 ns First SCLK pulse TNCSH SCLK falling to /SS rising 80 ns Last SCLK pulse TDIS Data in setup time 10 ns TDIH Data in hold time 10 ns Read Timing (VDD = VDD_IO = VDD_D = 3.3V, Temperature 25°C, CLOAD ≤ 50pF) TDOD Data out delay 20 ns TDOHZ Data out to high impedance delay 20 ns |
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