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RZ/A1M Datasheet(PDF) 74 Page - Renesas Technology Corp |
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RZ/A1M Datasheet(HTML) 74 Page - Renesas Technology Corp |
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74 / 137 page ![]() R01DS0479EJ0100 Rev.1.00 Page 74 of 137 Dec. 25, 2024 RZ/A1H Group, RZ/A1M Group 3. Electrical Characteristics Figure 3.17 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle) Tc1 Tr Tcw Td1 Tde t AD1 t AD1 t CSD1 t AD1 t RWD1 t RWD1 t CSD1 t AD1 t AD1 t AD1 tRDH2 t RDS2 t RASD1 t RASD1 Row address READA command Column address t CASD1 t CASD1 t BSD t BSD (High) t DQMD1 t DQMD1 t DACD t DACD Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. CKIO A25 to A0 CSn RD/ WR A12/A11 *1 D31 to D0 RAS CAS BS CKE DQMxx DACKn TENDn*2 |
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