MK50H25 datasheet(29/64 Pages) STMICROELECTRONICS

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4.2.3 Station Address and Control Field Filtering

The Local and Remote frame addresses may be either one or two octets according to the EXTA control

bit described in the MODE register. If extended address mode filtering is selected, bit zero of the ad-

dress field should be set to a zero if adherening to HDLC standards. If extended address filtering is not

selected, frame adresses should be located in the lower order byte of of their respective fields. The ad-

dress filtering is a one octet compare if the extended address bit, EXTA is 0 (Mode register bit 06), or fol-

lows the HDLC rules for extended addressing if EXTA is 1. Frames not matching either address are ig-

nored.

In the MK50H25, address filtering and control field handling applies only to octet aligned frames received

with good FCS. Any frame not meeting both of these conditions is discarded and the ”Bad Frames Re-

ceived” error counter (located at IADR + 38 of the Initialization Block ) is incremented.

Extended control field filtering is also possible using the EXTC bit (Mode Register bit 07), as shown in

Table 2 and Table 3. If EXTC is 0 then the C-field is one octet for all frames. If however EXTC is set to

1, the MK50H25 will look to see if either of the two least significant bits of the C-field is 0. If so, the frame

is said to have an extended control field which is two octets. In addition, bits EXTAF and EXTCF (Mode

the receiver will assume the address field to be two bytes long regardless of the first bit of the address

field. If EXTCF is set along with EXTC, the receiver will assume the contol field to be two bytes long re-

gardless of the first two bits of that field.

The following table shows the MK50H25 address filtering options and handling of the received Address

field.

In Transparent Mode, address filtering is supported if the PROM bit (CSR2, bit 10) is 0. In this case,

frames are accepted if the received Address field matches either the Send Frame Address or the Re-

ceive Frame Address as specified in the Initialization Block. The Send and Receive addresses may be

either one or two octets in length according to the EXTA control bit as described above. Frames not

matching either address are ignored. Bit RADR in the Receive Message Descriptor (RMD0 <09>)indi-

cates which of the two programmable adresses the frame matched. If address filtering is not used, these

fields can just be written as zeroes.

For global adresses, the XIDE bit is valid in transparent mode, depending upon the settings of the other

bits in the Mode Register, as shown in Table 3 below. If bit XIDE (CSR2, bit 08) is set to 1, then all

frames with address ”11111111” are accepted.

The following table shows the MK50H25 address filtering options and the way in which it handles the re-

ceived Address and Control fields in Transparent Mode.

Table 2: MK50H25 Address Filtering Options

NOTES:

1. PROM is defined in CSR2 bit 10. XIDE is defined in CSR2 bit 08.

2. DACE, EXTA, EXTAF, EXTC, and EXTCF are defined in the Mode register. X = Do not care.

3. DACE and PROM should be set =1 only in Transparent Mode operation.

EXTA

EXTAF

XIDE

PROM

DACE

ADDRESS FILTERING

Single octet filtering L&R (Local & Remote frame adresses)

No address filtering, all frames accepted

Single octet filtering L&R and global addresses

Not allowed

Double octet filtering L&R per HDLC rules

Double octet filtering L&R regardless of A-field LSB

Not allowed

MK50H25

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