S2-LPS datasheet(26/73 Pages) STMICROELECTRONICS

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DataRate=

fdig·DATARATE_M

232 if DATARATE_E=0

fdig· 216+DATARATE_M ∙2DATARATE_E

233

if DATARATE_E>0

fdig

8∙DATARATE_M if DATARATE_E =15

(13)

where

fdigisthedigitalclockfrequency.

In the cases where DATARATE_E<15, the actual modulator timing is generated by a fractional clock divider hence

is affected by a certain amount of jitter. In order to have a jitter free data rate generation a specific mode the last

equation must be used, DATARATE_E = 15 (for transmission only).

4.4.5

Receiver

The S2-LPS contains a low-power low-IF receiver able to amplify the input signal and provide it to the ADC with

a proper signal to noise ratio. The RF antenna signal is converted to a differential one by an external balun,

which performs an impedance transformation also. The receiver gain can be programmed to accommodate the

ADC input signal within its dynamic range. After the down-conversion at IF, a first order filter is implemented to

attenuate the out-of-band blockers.

4.4.5.1

Automatic frequency compensation

The automatic frequency compensation (AFC for short) algorithm allows compensating, within certain limits, a

relative frequency error between the transmitting device and the receiving one caused by for example from crystal

inaccuracies.

The AFC algorithm is operational only for frequency modulation such as 2-(G)FSK and 4-(G)FSK.

Due to the demodulation algorithm employed, any frequency error results in a DC offset in the demodulated signal

before slicing.

The basic operating principle of the AFC is that the minimum and maximum signal frequencies are detected and a

correction is calculated to remove the aforementioned offset.

Such correction is either applied at the slicer level in the form of offset compensation (default mode) or, optionally,

is used to adjust the second IF conversion stage frequency. The former mode allows a quick recovery of the

frequency error but does not prevent part of the received signal power to be cut by the channel filter; the latter

mode adjusts the signal frequency before entering the channel filter thus avoiding power loss but requires a

longer period to settle. The first mode is recommended for normal operation.

The AFC also provides the estimated frequency error through the AFC_CORR register. If the frequency error is

known to be constant (for example communication always occurs between the same pair of devices), this value

can directly be used to correct the programmed center frequency.

In order to guarantee both fast lock and smooth tracking, the AFC has a fast mode and a slow mode. The

AFC will start in fast mode as soon as the RSSI threshold is passed and will switch to the slow mode after a

programmable period.

The AFC is controlled by the following parameters:

•

RSSI threshold: this parameter sets the minimum signal power above which the AFC algorithm is started

(RSSI_TH register).

•

AFC fast gain log2: this parameter sets the loop gain in the fast mode (AFC0 register), the range allowed is

0..15.

•

AFC slow gain log2: this parameter sets the loop gain in the slow mode (AFC0 register), the range allowed is

0..15.

•

AFC fast period: this parameter sets the length of the fast period in number of samples (AFC1 register), the

range allowed is 0...255. The recommended setting for this parameter is such that the fast period equals

the preamble length. Since the algorithm operates typically on 2 samples per symbol, the programmed value

should be twice the number of preamble symbols. If this parameter is set to 0 then the switching from fast

to slow mode is controlled by the sync word detection, for example the fast gain is used before the sync

detection, the slow gain is used after sync detection.

•

AFC mode: this parameter sets the AFC correction mode (AFC2 register. 0b: slicer correction, 1b: 2nd IF

correction).

•

AFC enable: this parameter enables the AFC algorithm (AFC2 register).

S2-LPS

Digital modulator

DS13831 - Rev 1

page 26/73

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