RIVA128 datasheet(63/77 Pages) STMICROELECTRONICS

63 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

63/77

APPENDIX

Descriptions of register contents include an indication if register fields are readable (R) or writable (W) and

the initial power-on or reset value of the field (I). ‘-’ indicates not readable / writable, X indicates an inde-

terminate value, hence I=X indicates register or field not reset.

PCI CONFIGURATION REGISTERS

This section describes the 256 byte PCI configuration spaces as implemented by the RIVA 128. A single

PCI VGA device is defined by the RIVA 128 which decodes and acknowledges the first 256 bytes of the

configuration address space. The RIVA 128 does not respond (does not assert DEVSEL#) for functions

1-7.

A.1

Byte offsets 0x03 - 0x00

Device Identification Register (0x03 - 0x02)

Vendor Identification Register (0x01 - 0x00)

0x03

0x02

0x01

0x00

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits

Function

R W I

31:16

The DEVICE_ID_CHIP bits contain the chip number allocated by the manu-

facturer to identify the particular device.

= 0x0018

R - 0x0018

Bits

Function

R W I

15:0

VENDOR_ID bits allocated by the PCI Special Interest Group to uniquely

identify the manufacturer of the device.

NVIDIA/SGS-THOMSON Vendor ID = 0x12D2 (4818)

R - X

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