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ML22Q533 Datasheet(PDF) 4 Page - Rohm

Part # ML22Q533
Description  4-Channel Mixin g Speec h Synthesis LSIs with Built-in Flash M emor y fo r Automotive
PDF  178 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

ML22Q533 Datasheet(HTML) 4 Page - Rohm

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FEDL22Q53X-02
ML22Q53X
■ Pin Description
Pin
Symbol
I/O
Attribute
Description
Initial
value
*1
1,25
DGND
G
-
Digital ground pin.
—
2
SCL
I
-
I
2C slave serial clock pin.
When using an I
2C, be sure to insert a pull-up resistor between DV
DD
pin.
Accessing with clock synchronous serial interface at the same time is
prohibited.
H
3
SDA
IO
-
I
2C slave serial data input/output pin.
When using an I
2C, be sure to insert a pull-up resistor between DV
DD
pin.
Output: Nch MOS OPEN DRAIN output
Input: High-impedance input
Accessing with clock synchronous serial interface at the same time is
prohibited.
H
4
LRCLK
I
-
SAI word clock input pin.
L
5
BCLK
I
-
SAI bit clock input pin.
L
6
SAI_IN
I
-
SAI bit data input pin.
The data are loaded at the rising edges of BCLK.
L
7
SAI_OUT
O
-
SAI bit data output pin. Output data at the falling edge of BCLK.
L
8
CSB
I
Negative
Clock synchronous serial interface chip select pin.
The SCK and SI inputs are accepted only when this pin is at the "L"
level.
Accessing with I
2C slave interface at the same time is prohibited.
H
9
SCK
I
-
Clock synchronous serial interface clock input pin.
Accessing with I
2C slave interface at the same time is prohibited.
L
10
SI
I
-
Clock synchronous serial interface data input pin.
Data is fetched in synchronization with SCK.
Accessing with I
2C slave interface at the same time is prohibited.
L
11
SO
O
-
Clock synchronous serial interface data output pin.
When the CSB pin is at an "L" level, data is output in synchronization
with SCK.
When the CSB pin is at an "H" level, this pin enters a high-impedance
state.
Accessing with I
2C slave interface at the same time is prohibited.
Hi-Z
13
IRCSB
I
Negative
Flash memory interface chip select input pin.
Input the "H" level during non-access and the "L" level during access.
Setting the IRON pin to "H" enables input.
H
14
IRSCK
I
-
Flash memory interface serial clock input pin.
Setting the IRON pin to "H" enables input.
H
15
IRSO
O
-
Flash memory interface serial data output pin.
Setting the IRON pin to "H" enables output.
Hi-Z
*2
16
IRSI
I
-
Flash memory interface serial data input pin.
Setting the IRON pin to "H" enables input.
L
17
IRON
I
Positive
Pin to enable the flash memory interface.
When this bit is set to "L", the flash memory interface pin is disabled. A
pull-down resistor is internally connected to the LSI.
Set this bit to "L" during playback operation using flash memory.
Setting this bit to "H" allows rewriting of the flash memory using the
flash memory interface.
Set this bit to "H" for onboard rewriting.
L
*1 Initial value at reset input and power-down. The pin whose IO is "I" indicates a fixed level from outside.
*2 IRON pin "L" setting status
4/178



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