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ST10F163

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XVI.4.13 - External bus arbitration

1. The ST10F163 will complete the currently running bus cycle before granting bus access.

2. This is the first possibility for BREQ to get active.

3. The CS outputs will be resistive high (pullup) after

64.

VDD =5 V ± 10%

VSS =0 V

TA = 0 to +70 °C

CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

CL (for Port 6, CS) = 100 pF

Parameter

Symbol

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

min.

max.

min.

max.

HOLD input setup time to CLKOUT

t61

–20–

CLKOUT to HLDA high or BREQ low delay

t62

–20–20

CLKOUT to HLDA low or BREQ high delay

t63

–20–20

CSx release

t64

–20–20

CSx drive

t65

-4

Other signals release

t66

–20–20

Other signals drive

t67

-4

Figure 23 : External bus arbitration, releasing the bus

CLKOUT

HOLD

t61

HLDA

t63

Other

Signals

t66

CSx

(On P6.x)

t64

BREQ

t62

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