ST10F168-Q3 datasheet(53/74 Pages) STMICROELECTRONICS

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6. During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference

voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results

from the programmed conversion timing.

7. Partially tested, guaranteed by design characterization.

8. To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at

the ADC input. The cut-off frequency of this filter must be twice the highest conversion frequency used in the application as described

in the formula:

fcut-off = 2 / tc app

where tc app is the shorter conversion time used in the application, calculated with the following formula:

tc app = 14 tCC + tS + 4 TCL (= 14 tCC + 2 tSC + 4 TCL).

ADC Sample time and conversion time are programmable. The table below should be used to calculate

the above timings.

20.5 - AC Characteristics

20.5.1 - Test Waveforms

Conversion Time

Sample Time

ADCON.15|14 (ADCTC)

Conversion clock tCC

ADCON.13|12 (ADSTC)

Sample clock tSC

TCL x 24

tCC

Reserved, do not use

tCC x 2

TCL x 96

tCC x 4

TCL x 48

tCC x 8

Figure 16 : Input / output waveforms

Figure 17 : Float waveforms

2.4V

0.45V

Test Points

0.2VDD+0.9

0.2VDD-0.1

AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.

Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

Timing

Reference

Points

VLoad +0.1V

VLoad -0.1V

VOH -0.1V

VOL +0.1V

VLoad

VOL

VOH

For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.

It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).

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