ST72141K datasheet(69/132 Pages) STMICROELECTRONICS

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ST72141K

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MOTOR CONTROLLER (Cont’d)

Table 27. Step Ratio Update

CONTROL REGISTER A (MCRA)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = MOE:

Output Enable bit.

0: Outputs and Clocks disabled

1: Outputs and Clocks enabled

Bit 6 = RST:

Reset MTC registers.

Software can set this bit to reset all MTC registers

without resetting the ST7.

0: No MTC register reset

1: Reset all MTC registers

Bit 5 = SR:

Sensor ON/OFF.

0: Sensorless mode

1: Sensor mode

Table 28. Sensor Mode Selection

Bit 4 = DAC:

Direct Access to phase state register.

0: No Direct Access (reset value). In this mode all

the registers with a preload register are taken

into account at the C event.

1: Direct Access enabled. In this mode, write a val-

ue in the MPHST register to access the outputs

directly. All other registers with a preload regis-

ter are taken into account at the same time.

Table 29. DAC Bit Meaning

Note 1: When the MTC clock is disabled, the

MTIM counter is not reset but as in this case it is in

write access, a reset can be done by software.

Note 2: In direct access mode, only logical levels

(0 or 1) can be output on the MCOx pins. There is

no PWM signal generation in this mode.

Bit 3 = V0C1:

Voltage/Current Mode

0: Voltage Mode

1: Current Mode

Bit 2 = SWA:

Switched/Autoswitched Mode

0: Switched Mode

1: Autoswitched Mode

Table 30. Switched and Autoswitched Modes

Bit 1 = CFF:

Current Feedback Filter

0: Current Feedback Filter disabled

1: Current Feedback Filter enabled

Bit 0 = DCB:

Data Capture bit

0: Use MZPRV (ZN-1) for multiplication

1: Use MZREG (ZN) for multiplication

MOE

bit

SWA

bit

Clock

State

Read

Ratio

Increment

(Slow Down)

Ratio

Decrement

(Speed-Up)

Disa-

bled

Al-

ways

possi-

ble

Write the ST[3:0] value di-

rectly in the MPRSR register

Ena-

bled

Set RPI bit in

the MISR reg-

ister till next

commutation

Set RMI bit in

the MISR reg-

ister till next

commutation

Ena-

bled

Updated automatically ac-

cording to MZREG value

MOE

RST

DAC

V0C1

SWA

CFF

DCB

MOE bit

MCO[5:0] Output pin

State

Tristate

Output enabled

bit

Mode

OS2 bit

enable

Behaviour of the output

PWM

Sensors not

used

OS2

enabled

“Before D” behaviour & “af-

ter D” behaviour

Sensors

used

OS2

disabled

Only “after D” behaviour

MOE

bit

DAC

bit

Effect on Output

Effect on MTIM

Timer

High Z

Clock disabled

Standard

running mode

Standard running

mode

MPHST register value

(depending on MPOL

Clock disabled

SWA

bit

Commutation Type

MCOMP Register

access

Switched mode

Read/Write

Autoswitched mode

Read only

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