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TAS5705PAPR Datasheet(PDF) 49 Page - Texas Instruments |
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TAS5705PAPR Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 71 page ![]() CLOCK CONTROL REGISTER (0x00) DEVICE ID REGISTER (0x01) TAS5705 www.ti.com ...................................................................................................................................................................................................... SLOS549 – JUNE 2008 In the manual mode, the clock control register provides a way for the system microprocessor to update the data and clock rates based on the sample rate and associated clock frequencies. In the autodetect mode, the clocks are automatically determined by the TAS5705. In this case, the clock control register contains the autodetected FS and MCLK status as automatically detected (D7–D2). Bits D7–D5 select the sample rate. Bits D4–D2 select the MCLK frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must be written to D0 to inform the DAP that the written clocks are valid. Table 8. Clock Control Register (0x00) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 – – – – – fS = 32-kHz sample rate 0 0 1 – – – – – fS = 38-kHz sample rate 0 1 0 – – – – – fS = 44.1-kHz sample rate 0 1 1 – – – – – fS = 48-kHz sample rate (1) 1 0 0 – – – – – fS = 88.2-kHz sample rate 1 0 1 – – – – – fS = 96-kHz sample rate 1 1 0 – – – – – fS = 176.4-kHz sample rate 1 1 1 – – – – – fS = 192-kHz sample rate – – – 0 0 0 – – MCLK frequency = 64 × fS (2) – – – 0 0 1 – – MCLK frequency = 128 × fS (3) – – – 0 1 0 – – MCLK frequency = 192 × fS – – – 0 1 1 – – MCLK frequency = 256 × fS (1) – – – 1 0 0 – – MCLK frequency = 384 × fS – – – 1 0 1 – – MCLK frequency = 512 × fS (4) – – – 1 1 X – – Reserved – – – – – – 0 – Bit clock (SCLK) frequency = 64 × fS or 32 × fS (selected in register 0x04) (1) – – – – – – 1 – Bit clock (SCLK) frequency = 48 × fS (5) – – – – – – – 0 Clock not valid (in manual mode only) (1) – – – – 1 Clock valid (in manual mode only) (1) Default values are in bold. (2) Rate not available for 32-, 44.1-, and 48-kHz data rates (3) Rate not available for 32-kHz data rate (4) Rate not available for 176.4-kHz and 192-kHz data rates (5) Rate only available for 192-fS and 384-fS MCLK frequencies The device ID register contains the ID code for the firmware revision. Table 9. General Status Register (0x01) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 – – – – – – – Default (1) – 0 1 0 0 0 0 1 Identification code (1) Default values are in bold. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Link(s): TAS5705 |
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