ADN8102ACPZ-R7 datasheet(28/32 Pages) AD

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ADN8102

Rev. A | Page 28 of 32

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

POWER SUPPLY CONNECTIONS AND GROUND

PLANES

Use of one low impedance ground plane is recommended.

The VEE pins should be soldered directly to the ground plane

to reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance. The exposed pad should be connected to the VEE

plane using plugged vias so that solder does not leak through

the vias during reflow.

Use of a 10 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

printed circuit board (PCB). It is recommended that 0.1 μF and

1 nF ceramic chip capacitors be placed in parallel at each supply

pin for high frequency power supply decoupling. When using

0.1 μF and 1 nF ceramic chip capacitors, they should be placed

between the IC power supply pins (VCC, VTTI, and VTTO)

and VEE, as close as possible to the supply pins.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be realized by using close spacing

between the planes. This capacitance is given by

CPLANE = 0.88εr × A/d (pF)

where:

εr is the dielectric constant of the PCB material.

A is the area of the overlap of power and GND planes (cm2).

d is the separation between planes (mm).

For FR4, εr = 4.4, and 0.25 mm spacing, C ≈ 15 pF/cm2.

TRANSMISSION LINES

Use of 50 Ω transmission lines is required for all high frequency

input and output signals to minimize reflections. It is also necessary

for the high speed pairs of differential input traces to be matched in

length, as well as the high speed pairs of differential output traces,

to avoid skew between the differential traces.

SOLDERING GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the LFCSP are rectangular. The PCB pad for these

should be 0.1 mm longer than the package land length and

0.05 mm wider than the package land width. Center the land on

the pad, which ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central exposed pad.

The pad on the PCB should be at least as large as this exposed pad.

The user must connect the exposed pad to VEE using plugged vias

so that solder does not leak through the vias during reflow. This

ensures a solid connection from the exposed pad to VEE.

ADN8102ACPZ-R7 Datasheet(PDF) 28 Page - Analog Devices

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