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ADP130AUJZ-2.5-R7 Datasheet(PDF) 14 Page - Analog Devices

Part # ADP130AUJZ-2.5-R7
Description  350 mA, Low VIN, Low Quiescent Current, CMOS Linear Regulator
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP130AUJZ-2.5-R7 Datasheet(HTML) 14 Page - Analog Devices

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ADP130
Rev. 0 | Page 14 of 20
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
(1)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
COUT = 0.94 μF at 1.8 V, as shown in Figure 36.
Substituting these values in Equation 1 yields the following:
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over tempera-
ture and tolerance at the chosen output voltage.
To guarantee the performance of the ADP130, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP130 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.1 V. This ensures that the ADP130 inputs
and the output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP130 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 37,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
CH1 500mV
CH2 500mV
M10ms
A CH2
640mV
1
T 30%
2
–VOUT = 1.8V
CIN = COUT = 1µF
VOUT
500mV/DIV
EN
500mV/DIV
Figure 37. Typical EN Pin Operation
As shown in Figure 37, the EN pin has built-in hysteresis. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active and inactive thresholds are derived from the
VIN voltage. Therefore, these thresholds vary with changing input
voltage. Figure 38 shows typical EN active and inactive thresholds
when the VBIAS voltage varies from 2.3 V to 5.5 V.
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VBIAS (V)
EN ACTIVE
EN INACTIVE
Figure 38. Typical EN Pin Thresholds vs. Input
The ADP130 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 0.8 V option
is approximately 180 μs from the time at which the EN active
threshold is crossed to when the output reaches 90% of its final
value. The start-up time depends somewhat on the output voltage
setting and increases slightly as the output voltage increases.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
100
200
300
400
500
600
700
800
900 1000
TIME (µs)
VBIAS = 2.3V
VIN = 3.6V
ILOAD = 10mA
ENABLE
3.0V
1.8V
1.2V
0.8V
Figure 39. Typical Start-Up Time



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