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AT89C5132-ROTUL Datasheet(PDF) 78 Page - ATMEL Corporation |
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AT89C5132-ROTUL Datasheet(HTML) 78 Page - ATMEL Corporation |
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78 / 182 page ![]() 78 4173E–USB–09/07 AT89C5132 Reset Value = 0000 0000b Table 64. UEPINT Register UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register Reset Value = 0000 0000b Table 65. UEPIEN Register UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register Bit Number Bit Mnemonic Description 7 - 4 - Reserved The values read from these Bits are always 0. Do not set these Bits. 3 EP3RST Endpoint 3 FIFO Reset Set and clear to reset the endpoint 3 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. 2 EP2RST Endpoint 2 FIFO Reset Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. 1 EP1RST Endpoint 1 FIFO Reset Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. 0 EP0RST Endpoint 0 FIFO Reset Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. 7 6 5 4 3 2 1 0 - - - - EP3INT EP2INT EP1INT EP0INT Bit Number Bit Mnemonic Description 7 - 4 - Reserved The values read from these Bits are always 0. Do not set these Bits. 3 EP3INT Endpoint 3 Interrupt Flag Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 3 interrupt is enabled in UEPIEN. Must be cleared by software. 2 EP2INT Endpoint 2 Interrupt Flag Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 2 interrupt is enabled in UEPIEN. Must be cleared by software. 1 EP1INT Endpoint 1 Interrupt Flag Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 1 interrupt is enabled in UEPIEN. Must be cleared by software. 0 EP0INT Endpoint 0 Interrupt Flag Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 0 interrupt is enabled in UEPIEN. Must be cleared by software. 7 6 5 4 3 2 1 0 - - - - EP3INTE EP2INTE EP1INTE EP0INTE |
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