STLC5466 datasheet(67/130 Pages) STMICROELECTRONICS

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STLC5466

VI.39 - Address Field Recognition Address Register 2

AFRAR2 (5C)H

The write operation is launched when AFRAR2 is written by the microprocessor.

VI.40 - Address Field Recognition Data Register 2

AFRDR2 (5E)H

The value of the first received byte must be equal to all “1”s and the value of the

second received byte must be equal to “1” also.

The value of the first received byte must be equal either to that of AF0/7 or to “1”

and the value of the second received byte must be equal to all “1”s.

The value of the second received byte must be equal either to that of AF8/15 or to

all “1”s.

The value of the first received byte must be equal to that of AF0/7 bits and the value

of the second received byte must be equal either to that of AF8/15 or to all “1”s.

The value of the first received byte must be equal to “1” and the value of the second

received byte must be equal either to that of AF8/15 or to all “1”s.

The value of the first received byte must be equal either to that of AF0/7 or to “1”

and the value of the second received byte must be equal either to that of AF8/15 or

to all “1”s.

bit15

bit8

bit7

bit0

CH4

CH3

CH2

CH1

CHO READ AMM

After reset (0000)H

AMM

Access to Mask Memory

AMM=1, Access to Address Field Recognition Mask Memory.

AMM=0, Access to Address Field Recognition Memory.

READ

READ ADDRESS FIELD RECOGNITION MEMORY

READ=1, READ AFR MEMORY.

READ=0, WRITE AFR MEMORY.

CH0/4

In reception these five bits define one of 32 channels of the second 32 HDLC Controller 2 named HDLC 2

connected to Din6/Dout6 of the switching matrix.

bit15

bit8

bit7

bit0

AF15/

AFM15

AF14/

AFM14

AF13/

AFM13

AF12/

AFM12

AF11/

AFM11

AF10/

AFM10

AF9/

AFM9

AF8/

AFM8

AF7/

AFM7

AF6/

AFM6

AF5/

AFM5

AF4/

AFM4

AF3/

AFM3

AF2/

AFM2

AF1/

AFM1

AF0/

AFM0

After reset (0000)H

AF0/15

ADDRESS FIELD BITS if AMM=0 (AMM bit of AFRAR 2

AF0/7; First byte received; AF8/15: Second byte received.

These two bytes are stored into Address Field Recognition Memory when AFRAR2 is written by the mi-

croprocessor(AMM=0).

AFM0/

ADDRESS FIELD BIT MASK0/15 if AMM=1 (AMM bit of AFRAR 2)

AMF0/7. When AR10=1 (See HRCR2) each bit of the first received byte is compared respectively to AFx

bit if AFMx=0. In case of mismatching, the received frame is ignored. If AFMx=1, no comparison between

AFx and the corresponding received bit.

AMF8/15. When AR20=1 (See HRCR2) each bit of the second received byte is compared respectively to

AFy bit if AFMy=0. In case of mismatching, the received frame is ignored. If AFMy=1, no comparison be-

tween AFy and the corresponding received bit.

These two bytes are stored into Address Field Recognition Mask Memory when AFRAR 2 is written by

the microprocessor (AMM=1).

Second Byte

First Byte

Conditions to Receive a Frame

AR21

AR20

AR11

AR10

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